VLSI Design and Physical Layout of a Decade Counter Digital IC Using an Open-Source CAD Tool

Abstract

Integrated circuits (ICs) are the foundation of modern electronics, and developing the capability to design and implement ICs is crucial for technological advancement and security. This paper presents the full-custom design, simulation,
and physical layout of a decade counter (divide-by-10 counter) using an open-source VLSI CAD tool within the context of a
resource-constrained educational system. The decade counter is implemented with a CMOS logic architecture and targeted for
fabrication in the ON Semiconductor C5 0.5 µm CMOS process via the MOSIS service. The design flow spans initial specification
and behavioral modeling through circuit schematic, layout design, and final verification. The open-source Electric VLSI CAD system
is used for all design steps, including schematic capture, layout editing, design rule checking (DRC), and layout-versus-schematic
(LVS) verification. SPICE simulations (using Electric’s built-in LTspice engine) are performed at both the schematic and post-
layout levels to validate functionality and performance. The finalized layout (GDSII) was generated for mask fabrication, and
the design passes all DRC and LVS checks. Key results show that the counter meets its target specifications: it correctly cycles
through 10 states (0–9) with a measured propagation delay of 63 ns (vs. 60 ns target) and power dissipation of 16 µW (vs. 15 µW target) at 5 V supply. The core layout occupies approximately 1.5 mm × 3.2 mm, within the allotted area budget.
This work demonstrates a successful proof-of-concept IC design using affordable, open-source tools and discusses the
methodology, verification techniques, and iterative optimizations employed. It serves as a case study in building local VLSI design
capacity and lays a foundation for more complex chip design projects in academic and low-resource settings.